Introduction

Silicon carbide is a polytypic compound: depending on the stacking sequence of the silicon–carbon bilayers along the crystallographic direction, more than two hundred polytypes may occur. Among the common polytypes are 2H, 4H, 6H, 15R and 3C. Of these, 4H-SiC is preferred for high-voltage, high-temperature and high-power devices, because it offers a higher critical avalanche breakdown field, higher electron saturation velocity and a wider band-gap, making it the ideal material and the primary target of current industrial deployment.

Nevertheless, during the growth of 4H-SiC single crystals one routinely encounters defects such as polytype inclusions, inclusions/particles, micropipes and dislocations—factors that severely limit single-crystal yield. Since the substrate alone accounts for approximately 47 % of the total cost in the SiC device supply chain, reducing crystal defect density and improving growth yield constitute the principal route to large-scale industrialization of SiC.

1. PVT Method for SiC Single Crystal Growth

The Physical Vapor Transport (PVT) method is the mainstream approach for SiC single crystal fabrication. As illustrated in Figure 1, a typical PVT setup consists of a quartz chamber, heating system (induction or graphite heater), graphite felt insulation, graphite crucible, SiC seed crystal, SiC powder, and a high-temperature thermocouple.

During the process, the SiC powder placed at the bottom of the crucible is heated to 2100–2400 °C, causing it to decompose into gaseous species such as Si, Si₂C, and SiC₂. Under the combined influence of temperature and concentration gradients, these vapor species are transported upward and condense on the relatively cooler seed crystal surface, where nucleation and crystal growth occur.

Key Technical Considerations

Purity of graphite components:
The purity of graphite materials used in the hot zone must meet stringent standards. Graphite parts should contain < 5 × 10⁻⁶ impurities, and graphite felt < 10 × 10⁻⁶. Boron (B) and aluminum (Al) concentrations must be < 0.1 × 10⁻⁶, as these elements act as hole sources, leading to unstable electrical performance and crystal defects.

Seed crystal polarity selection:
The C-face (0001) is suitable for 4H-SiC growth, while the Si-face (0001) is used for 6H-SiC.

Off-axis seed crystal utilization:
A 4° off-axis seed orientation promotes uniform growth, minimizes defects, and stabilizes the 4H polytype by guiding the growth direction and reducing internal stress.

Seed bonding technique:
A dense carbonized interlayer (~20 μm) is formed by coating the Si-face with photoresist and carbonizing it at ~600 °C, then bonding to graphite paper or plates under heat and pressure. This method prevents backside ablation and improves crystal integrity.

Interface stability during growth:
As the crystal thickens, the growth interface gradually moves toward the SiC powder surface, altering the local thermal and chemical environment. To maintain a stable interface, crucible lifting mechanisms can be employed to maintain a consistent axial and radial temperature gradient.

2. Key Technologies for SiC Crystal Growth

2.1 SiC Powder Doping with Cerium (Ce)

Doping SiC powder with Ce elements effectively stabilizes the 4H-SiC polytype and enhances growth rate and uniformity. Ce doping suppresses impurity incorporation, reduces defect formation, and improves resistivity uniformity. Common Ce sources include CeO₂ and CeSi₂, with the latter yielding crystals of lower resistivity.

To achieve spatial and temporal uniformity, Ce-containing silicide is pre-synthesized and then mixed with high-purity SiC powder. During sublimation, Ce is gradually released, ensuring continuous and homogeneous doping, stabilizing 4H-SiC growth throughout the process.

2.2 Axial and Radial Temperature Gradient Control

The SiC growth temperature field comprises both radial and axial gradients.

Radial gradients influence crystal shape and polytype formation — excessive gradients lead to stacking faults, polytype transitions (6H, 15R), and surface curvature irregularities.

Axial gradients affect growth rate and uniformity — gradients that are too small can cause unwanted nucleation and slower vapor transport.

Optimization strategies include:

Adjusting crucible geometry to achieve uniform radial distribution while increasing axial gradients;

Modifying external insulation design;

Fine-tuning crucible position within the thermal field using thermal simulation software.

2.3 Basal Plane Dislocation (BPD) Control

BPDs occur when shear stress exceeds the critical threshold during growth or cooling, activating slip systems. These defects degrade pn-junction diodes under forward bias and increase leakage current in MOSFETs and JFETs during blocking operation.

Key suppression measures:

Control the cooling rate during late-stage crystal growth;

Optimize seed bonding to ensure stable axial temperature gradients;

Use graphite crucibles with thermal expansion coefficients matching SiC.

Fast cooling and optimized bonding reduce BPD density by preventing temperature fluctuations and backside erosion.

2.4 Gas Phase Composition (C/Si Ratio) Control

Maintaining a carbon-rich vapor environment (high C/Si ratio) is crucial for stabilizing 4H-SiC growth, as it suppresses step bunching and polytype transitions. At higher temperatures, the gas phase naturally shifts toward a carbon-rich condition; however, beyond 2100 °C, 4H-SiC tends to convert to 6H-SiC.

Control methods include:

Maximizing crucible bottom temperature to enhance SiC powder sublimation;

Using high-porosity graphite crucibles that act as additional carbon sources;

Introducing porous graphite plates or liners to further increase the C/Si ratio.

2.5 Low-Stress Growth Control

Excess internal stress during growth leads to crystal bending, cracking, and increased BPD density, which degrades device performance during epitaxy.

Stress reduction strategies include:

Optimizing the thermal field for near-equilibrium growth;

Redesigning crucible geometry for freer crystal expansion;

Allowing a ~2 mm gap between seed and graphite holder to accommodate thermal expansion;

Employing in-furnace annealing with controlled temperature and duration to release residual stress.

3. Development Trends in SiC Crystal Growth

The future development of high-quality SiC single crystal growth is expected to progress in the following directions:

Larger Diameter Crystals
SiC crystals have evolved from millimeter-scale to 6-inch, 8-inch, and even 12-inch wafers. Larger sizes improve manufacturing efficiency and reduce costs while meeting high-power device requirements.

Higher Crystal Quality
Although crystal quality has significantly improved, defects such as micropipes and dislocations remain. Further enhancement requires advanced doping, interface control, and defect suppression techniques.

Lower Production Costs
Since substrates account for nearly half of total device cost, optimization of growth parameters, increased yield, and reduced raw material expenses are critical to achieving cost-effective production.

Intelligent Growth Systems
With the advancement of AI and big data technologies, SiC growth systems will become increasingly automated and intelligent. Real-time sensing, process monitoring, and data-driven optimization will enhance growth stability, reproducibility, and crystal quality.

Conclusion

This article provides a comprehensive overview of high-quality SiC single crystal growth technology. It discusses fundamental SiC properties, PVT growth mechanisms, key process parameters affecting crystal quality, and advanced defect control methods. Furthermore, it outlines the future direction of SiC crystal growth toward larger size, higher quality, lower cost, and intelligent manufacturing.

In summary, the preparation of high-quality SiC single crystals remains a central focus in semiconductor material research. As technological progress continues, SiC crystal growth techniques will become increasingly refined, laying a solid foundation for its application in high-temperature, high-frequency, and high-power electronic devices.
 

✅ About JXT Technology Co., Ltd.
JXT Technology Co., Ltd. supplies 2-inch to 8-inch SiC wafers with customizable thickness and dimensions. Precision cutting and tailored wafer specifications are available to meet various application requirements.